1. Field of the Invention
The present invention relates to an SRTS receiver for reproducing the user signal clock at a receiving party, by means of SRTS (Synchronous Residual Time Stamp) used to transfer the bit rate information of a user signal from a sending party to a receiving party, when an ATM cell accommodates a CBR (Constant Bit Rate) signal asynchronous with a network as the user signal by the AAL Type1.
2. Description of the Related Art
The SRTS is a method defined by ITU-T recommendation I. 363. In a sending party, the frequency ratio between the bit rate of a CBR user signal and a reference clock derived from a network clock is measured, expressed as the RTS (Residual Time Stamp) information of four bits, and transferred to a receiving party by use of the CSI bit within the SAR-PDU header of AAL Type 1. In the receiving party, according to the received 4-bit RTS information, the user signal clock is reproduced, by use of the reference clock derived from the same network clock as the sending party.
The conventional SRTS receiver will be described with reference to the drawings. FIG. 9 is a block diagram showing the constitutional example of a RTS information creating circuit shown in ITU-T recommendation I. 363, FIG. 10 is a block diagram showing the constitutional example of the conventional SRTS receiver, FIG. 11 is a flow chart showing the operation of the SRTS receiver shown in FIG. 10, and FIG. 12 is a block diagram showing the constitutional example of a PPL (phase locked loop) circuit in the SRTS receiver of FIG. 10.
First, the description will be made about the operation of the RTS information creating circuit of ITU-T recommendation I. 363 shown in FIG. 9. A reference clock derived from the network clock is supplied to an input terminal 911. The frequency of the reference clock is defined by the I. 363. A 4-bit counter 901 is activated upon receipt of a reference clock, divides the reference clock by 16-clock and supplies the output. The 4-bit counter 901 is free-running without being reset. The counted output value S91 of the 4-bit counter 901 is supplied to a D-flip flop circuit 903 via the signal line of four bits. While, the clock of the CBR user signal (user clock) is supplied to an input terminal 912. Upon receiving the user clock, a modulo N counter 902 is activated. The value "N" in the modulo N counter 902 means the number of bits of user signal during the transfer period of the RTS information. According to I. 363, the RTS information is to be transferred once in every eight cells. Since the SAR-PDU payload within eight cells is 3008 bits, if there is no other header (such as CS-PDU header), the value "N" becomes "3008". The modulo N counter 902 generates a pulse signal S92 every time N-counting the user clock. The pulse signal S92 is supplied to the D-flip flop circuit 903 of four bits. The D-flip flop circuit 903 samples four bits of the counted output value S91 of the 4-bit counter 901 according to the pulse signal S92. The sampled 4-bits information is called RTS information and is transferred from the output terminal 913 to the ATM channel.
Assuming that the reference clock frequency is defined as fnx and that the user clock frequency is defined as fs, the 4-bit counter 901 counts M=N.times.fnx/fs on average during the N-clock period of the user clock. Assuming that the integral part of M is defined as Mq, the 4-bit counter 901 actually counts Mq or Mq+1 and the average count number becomes M count during the N-clock period of the user clock.
This time, the description will be made about a SRTS receiver. As the conventional SRTS receiver, such a device is well known as disclosed in, for example, the article "Synchronous Techniques for Timing Recovery in BISND" (R. C. Lau and P. E. Fleischer, IEEE Transactions on Communications, Vol.43, No2/3/4, February/March/April, 1995) and the article "Jitter in Synchronous Residual Time Stamp" (K. Murakami, IEEE Transactions on Communications, Vol.44, No6, June 1996). FIG. 10 is a view showing the constitution of the SRTS receiver disclosed in the same articles. FIG. 11 is a time chart of the circuit of FIG. 10. Hereinafter, the operation of the device shown in FIG. 10 will be described with reference to FIG. 11.
In FIG. 10, the RTS information receiving means 1000 surrounded by the dotted line is a circuit portion for processing the received RTS information. At first, the operation of the RTS information receiving means 1000 will be described. The RTS information which is supplied from the output terminal 913 of the RTS information creating circuit shown in FIG. 9 to the input terminal 1011 via the ATM channel, is once stored into the FIFO circuit 1003 for absorbing the jitter delay in the ATM channel and read out sequentially. The 4-bit counter 1001 is activated by the reference clock received from the input terminal 1012 and it is free-running. The output signal S102 therefrom is supplied to a comparator 1004 together with the output signal S101 of the FIFO circuit 1003, where both signals are compared with each other. The comparator 1004 generates pulses when both signals coincide. The time chart of FIG. 11 shows the case where the value of the output signal S101 from the FIFO circuit 1003 is "5". As illustrated in FIG. 11, the output S103 of the comparator 1004 becomes train of pulses. On the other hand, the modulo ML counter 1002 is activated by the reference clock received from the input terminal 1012, stops when it counts ML pulses of the reference clock, and generates the gate signal S104. The gate circuit 1005, upon receipt of the gate signal S104 from the modulo ML counter 1002, operates to pass output pulse train S103 of the comparator 1004. When the gate circuit 1005 passes one pulse of the train, the gate output signal S105 is supplied and the modulo ML counter 1002 is reset, to stop the output of the gate signal S104. Simultaneously, the FIFO circuit 1003 restarts reading out new RTS information. The gate circuit 1005 always passes only one pulse out of the output pulse train S103 of the comparator 1004. Assuming that the value "ML" in the modulo ML counter 1002 is "Mq-8" according to I. 363, the interval of the output pulse S105 of the gate circuit 1005 becomes equal to Mq-clock cycle or Mq+1-clock cycle of the reference clock according to the received RTS.
FIG. 12 shows the constitutional example of the PLL circuit 1006 of FIG. 10. The PLL circuit 1006 of FIG. 12 comprises a phase comparator (PC) 1201, a direct-current amplifier (AMP) 1202, a voltage controlled oscillator (VCO) 1203, and a modulo N counter 1204. The interval of the gate output S105 supplied to the PLL 1006 in FIG. 10 is equal to the N-clock cycle of the user clock on average. Therefore, the signal obtained by the modulo N counter 1204 dividing the user clock by N, is supplied to the phase comparator (PC) 1201 and compared to the gate output S105.
The above-mentioned conventional SRTS receiver, however, has the following problems. When the ratio of the frequency division of the PLL circuit shown in FIG. 12 is "N", the value "N" usually becomes such a huge value as "3008" according to I. 363. The loop gain of the PLL circuit is inversely proportional to "N", and if the value "N" is large, the loop gain of the PLL circuit becomes extremely small. Generally, the PLL circuit deteriorates in various characteristics if the loop gain is small. Particularly, the characteristic of the phase noise suppression is deteriorated, and a phase noise generated by the voltage controlled oscillator appears in the output, thereby causing the deterioration in the quality of the reproduced user clock.
This will be shown by use of concrete numerical example. Assuming that the gain of the phase comparator 1201 is defined as K1[V/rad], the gain of the direct-current amplifier 1202 is defined as K2, and the conversion gain of the voltage controlled oscillator 1203 is defined as K3[rad/(sec.multidot.V)], the loop gain K is obtained by K=K1.times.K2.times.K3/N. Since the phase comparator 1201 represents the phase difference of, for example, 2.pi. [rad] by the voltage such as 2[V], the following expression can be obtained; K1=2/(2.pi.).apprxeq.0.318[V/rad]. The voltage controlled oscillator 1203 generally gains the conversion factor such as 100[ppm/V] if making use of a crystal oscillator. When the oscillation frequency is set to, for example, 44.736 MHz that is the DS3 bit rate in North America, K3 is obtained as K3=28.1.times.10.sup.3 [rad/(sec.multidot.V)]. The gain of the direct-current amplifier 1202 is set as, for example, K2=5, with small amplifier rate, so that the output of the direct-current amplifier 1202 would not be saturated. At this time, when N=3008, K=14.9. The loop gain K is equal to the jitter cut-off frequency of the PLL circuit, which is about 2.36[Hz]. However, the jitter cut-off frequency of the PLL circuit is preferably set to about 1 to 10 ppm of the oscillation frequency. If the jitter cut-off frequency becomes much smaller than this, the phase noise suppression characteristic will be deteriorated, and on the contrary, if it becomes larger than this, the input jitter suppression characteristic will be deteriorated. Accordingly, in this example, the jitter cut-off frequency is preferably within about 45 to 450 Hz. As is apparent from this, the loop gain in the above-mentioned numerical example (2.36[Hz]) is too small.
As a countermeasure to prevent such a situation, a method of increasing the gain of the direct-current amplifier 1202 may be considered, by way of example. However, in order to let the jitter cut-off frequency be 1 ppm of the oscillation frequency, it is necessary to fix the value of the gain K2 of the direct-current amplifier 1202 at around 1200. Then, since the output of the phase comparator 1201 varies in the range of 2[V], the output of the direct-current amplifier 1202 varies in the range of 2400[V]. Obviously, the direct-current amplifier 1202 would be saturated under this condition, and the PLL circuit will not perform the accurate operation at the frequency extraction time. As mentioned above, it is not preferable to prevent the decrease of the loop gain by increasing the gain of the direct-current amplifier 1202.
When the frequency division ratio of the PLL circuit is so large such as "3008", the conventional SRTS receiver cannot realize proper characteristics.